Pulse code modulated signal synchronizer

ABSTRACT

A bit synchronizer for a split phase PCM transmission which has first and second loop systems which respectively receive incoming phase coded PCM signals. In the first loop system the incoming bit signals are simultaneously supplied to two channels which alternately receive a generated, phase coded bit signal representative of a binary digit, and the generated bit signal is multiplied with the incoming bit signals. The multiplied signals are respectively integrated and held. When the incoming signal is properly phase locked with the generated bit signal, each channel will produce an integrated value which increases (either positively or negatively) over the entire bit period of the generated bit signal. The channels are respectively sampled at the end of one bit period and at the beginning of the following bit period. The sampled signals are supplied to a bit lock detector. If the bit period of the incoming signal is properly synced to the bit period of the supplied digit, the bit lock detector produces no output. If the bit periods are 180* out of phase, an error signal is produced to change the phase of the generated signal by 180*. In the second loop system the incoming bit signals are simultaneously supplied to two channels which alternatively receive a phase coded signal representative of a binary digit but phase shifted by 90* with respect to the first generated signal. The phase shifted signal is multiplied with incoming bit signals to null the phase and frequency of the generated signal in a phase locked relationship to the incoming signal where the phase lock can be either 0* or 180*. A counter means is used for timing of the generated signals and timing of sample intervals for each bit period so that the characteristics of the loops during the sample intervals are used as control signals until a 0* phase locked condition is reached.

United States Patent 1191 Kobayashi PULSE CODE MODULATED SIGNAL SYNCHRONIZER Herbert S. Kobayashi, Webster, Tex.

The United States of America as represented by the Administrator of the National Aeronautics and Space Administration, Washington, DC.

Filed: Nov. 8, 1972 Appl. No.: 304,705

[75] Inventor:

[73] Assignee:

US. Cl. 325/321, 325/419 Int. Cl. H04b 1/16 Field of Search 325/39, 41, 44,58, 419, 325/420, 60, 69, 321, 324, 320; 178/68, 69.5 R, 67, 88; 179/15 BS; 340/174.l H

References Cited UNITED STATES PATENTS 2 1972 Norris l78/68 X 7/1972 Melvin 178/67 x 9 1972 Mansfield et al. 325/60 X l/l97l Alexander et al 178/695 R [57] ABSTRACT A bit synchronizer for a split phase PCM transmission which has first and second loop systems which respec- 11.11 3,806,816 1 Apr. 23, 1974 tively receive incoming phase coded PCM signals. In the first loop system the incoming bit signals are simultaneously supplied to two channels which alternately receive a generated, phase coded bit signal representative of a binary digit, and the generated bit signal is multiplied with the incoming bit signals. The multiplied signals are respectively integrated and held. When the incomingsignal is properly phase locked with the generated bit signal, each channel will produce an integrated value which increases (either positively or negatively) over the entire bit period of the generated bit signal. The channels are respectively sampled at the end of one bit period and at the beginning of the following bit period. The sampled signals are supplied to a bit lock detector. If the bit period of the incoming signal is properly synced to the bit period of the supplied digit, the bit lock detector produces no output. If the bit periods are 180 out of phase, an error signal is produced to change the phase of the generated signal by 180. In the second loop system the incoming bit signals are simultaneously supplied to two channels which alternatively receive a phase coded signal representative of a binary digit but phase shifted by 90 with respect to the first generated signal. The phase shifted signal is multiplied with incoming bit signals to null the phase and frequency of the generated signal in a phase locked relationship to the incoming signal where the phase lock can be either 0 or 180". A counter means is used for timing of the generated signals and timing of sample intervals 8 Claims, 9 Drawing Figures i 1 210 i [M INTEGRATE ourPur 1 HOLDS DUMP SWITCH" STORAGE DATA 71 2 1 1 2 2 l i 1 1 i LOCK 7 A IM INTEGRATE sw11c11 STORAGE DET. 1 2 HOLD 2 DUMP i 37b 1 1 19 31 32 53 i 49 QM INTEGRATE 1 HOLD 2 DUMP I l 1 M 40 t1 1 l SWITCH MULZ-+ F/LTERV- vco gg 1 2 1 2 2 I 1 1 1 1 T I 1 in 7 11 I 43 64 45 46 .47 48 QM INTEGRATE 1 1 2 HOLD & DUMP ZATENTEDAPR23 I974 SHEET 3 BF 4 hsm mQm QQA 0cm mmm ism ME ME Dom PULSE CODE MODULATED SIGNAL SYNCI'IRONIZER ORIGIN OF THE INVENTION The invention described herein was madeby an employee of the United States'Government and may be manufactured and used by or for the Government of the United States of America for governmental purposes without the payment of any royalties thereon or therefor.

BACKGROUND OF THE INVENTION This invention relates to pulse code synchronizers and, more particularly, to pulse code synchronizers for timing split phase bits for decoding.

Transmission of data involves the choice of a medium or the actual data link and the choice of a format or the code for the transmitted intelligence. The medium for data transmission depends to a large extent on the physical location of the two devices. Where the devices are relatively closeto one another, electrical or mechanical means are used. Long distance transmissions are usually accomplished by radio which includes all forms of transmission that make use of the principles of electromagnetic radiation such as television, microwave, and radar. In a radio transmission there are typically two components the carrier wave and the intelligence (or data) signal which is incorporated into the 'carrier wave. The combining of the carrier wave and the data information for transmission is called modulation and, at the receiving station, the data information is separated from the carrier wave by a process called demodulation.

There are many ways or techniques or combining data information and carrier waves. The present invention concerns itself with the demodulation of a pulsetrain carrier with a pulse code and, more particularly, a split phase pulse code modulation. Modulation of a pulse carrier and pulse code is sometimes abbreviated as PCM. The pulse code is typically in a digital format where a series of binary digits or 1)'or bits comprise a word or data report and a number of words form a frame" which is a cycle of data compilation.

As an example of PCM transmission, a subcarrier frequency can be 8,l92 Hz. A suitable format is a single frame (a cycle of data compilation) at a rate of l Hz where each frame carriers 32 words (a data report). Each word can have a reporting capacity of eight bits (a digital value). Thus, with this example there is a bit rate of 256 bits per second. In this format the first and second words of a frame contain a 16-bit frame synchronizing code while the remaining words carry data information. For demodulation, the synchronizer must receive the input signals and synchronize a timing signal with the input signals to minimize the chance of obtaining erroneous information due to noise or intersymbol interference. The synchronizer output can be a serial code with timing signals which are supplied to a decommutator. The decommutator searches for the frame synchronizing pattern and, after acquiring word and frame synchronization, parallel data bits can be decommutated from the serial bit stream of the synchronizer.

SUMMARY OF THE INVENTION 0 nals having split phase bit coding are applied to each of the loop systems. In the frequency stabilizing loop system a frequenc generating means supplies pulse signals to a counter and logic circuit which, in turn,'provides timed outputs which include first and second pulse code modulated output signals each with a time phase shift relative to an in-phase pulse coded modulated signal. These phase shifted, alternating output signals are supplied to an analog multiplier where the generated signals are multiplied with the incoming signals. The multiplication product is integrated and sampled periodically at regular bit time intervals. The multiplication of these signals will produce an error signal if the frequency of the generated signal and the incoming signals are different. The error signal adjusts the frequency generating means to the frequency of the incoming carrier signal. When the frequency of the frequency generating means is established to that of the carrier, there are a number of null points where the error signal to the frequency generating means is stabilized and where the incoming signals and the signals of the frequency generating means are the same. Between the nullpoints for signals at the same frequency, there is a phase error signal for placing the generated signal for a bit in either a 0 or locked phase condition relative to an incoming bit.

The counter and logic circuit which provides a timing function relative to the bit period also supplies the inphase pulse code modulated signal to the phase sensing loop system. In the phase sensing loop system are two channels, each of which alternately integrates and holds the multiplication product of the incoming bit signal and the in-phase bit signal. Sampling signals supplied from the counter sample each of the loop circuits twice for each bit period. By comparing the sample values just before and just after a timing bit period, it can be determined if theincoming bit is in place with the bit function produced for the loop circuits. If the incoming bit period is not in phase with the generated bit signal, the phase of the generated signal is shifted by 180 to provide an in-phase condition.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic overview of a system embodying the present invention;

FIG. 2 is a representation of various signal waveforms which are illustrated for explanation purposes;

FIG. 3 is a schematic illustration of a circuitry arrangement embodying the present invention;

FIG. 4 is a representation of various timing signal waveforms for the circuitry of FIG. 3;

FIGS. 5 and 6 respectively are representations of various signal waveforms for the circuitry of FIG. 3 which are in-phase and 180 out of phase;

FIGS. 7 and 8 respectively are representations of various signal waveforms forthe circuitry of FIG. 3 which are in-phase and 180 out of phase; and V DETAILED DESCRIPTION OF THE INVENTION Referring to FIG. 1, a station for receiving a radio transmission is schematically illustrated. At the station is an antenna which picks up or detects radio transmission of an electrical signal comprising a Pulse Code Modulated wave train (hereinafter sometimes abbreviated and referred to as PCM"). The electrical signals are supplied to a receiver 11 for' amplification and detection of the incoming signals. A filter 12 further processes thesignals to eliminate undesired signals of other frequencies and noise components. In connection with the present invention, the PCM signal consists of characteristic signal where a number of digital bits (a binary digit 0 or l comprise a word, and a number of words form a frame and each frame carries coded information or data for a single measurement scan or cycle.

Relative to the pulse coding, each frame carries various data in a fixed relationship, and the first two words are typically used to synchronize the frame, that is, align the pulse input relative to a time base for correctly interpreting the O and 1 bits of each word and frame. The proper decoding of a split-phase PCM signal requires that the group of signals constituting words are properly synchronized. Thus, from the filter 12 an incoming signal is supplied to a bit synchronizer 13 which provides an output signal synchronized to all of the bits of a frame. A decommutator 14 receives a properly synced data frame and if any data appears erroneous it is because the data word is wrong and not because of erroneous detection of the input signal.

To illustrate how important synchronization is for this type of decoding, an illustration is provided in FIG. 2. As shown in FIG. 2(a), the waveforms between times I 4 and 1 -1,, illustrate digits of value l and the waveform between time t -t illustrates a digit of value 0. These waveforms are for split phase coding, i.e., a l value for a bit period P has an initial half-bit period P/2 in which the signal is positive relative to last half-bit period. A 0 valve has just the reverse where the initial half-bit period of the signal is negative relative to the last half-bit period.

In FIG. 2(b), the waveform as illustrated in FIG. 2(a) is shifted to the left by one-half of the bit time period. On a time basis, with the same waveform as in FIG. 2(a), the bit representation between times t -t and t -t, changes its binary value from a l to a 0. The data information between times t t is lost. Thus, at the receiving station if the bit signals are shifted in phase or time during the detection process, erroneous bit values are produced and bit values are lost.

With the phase coded signal as above described, synchronization of the words is necessary for proper decoding of the signal. Thus, a bit sync circuit 13 (FIG. 1) receives the sync words of a frame and locks the frame in the sync circuit. The decom circuit then receives the bits in proper order and provides the proper "word" output if the data of the bits is correct. In any event, error due to signal shift is eliminated.

A considerable concern for this type of system is that the input synchronizing word is properly synchronized or locked in proper phase relationship so that the resulting output is correctly interpreted. Whe'n synchronization of the input word is obtained, it is desirable to lock the reception to prevent drift and jitter i.e., the decom need not be required to reset the bit synchronized and thus lose input data.

Before going into the details of the structure embodying the present invention, it may be helpful to consider the mechanics of the process for obtaining the synchronized bit output. The incoming signal represents 0" or 1" digit values in a split phase mode. The synchronizer must detect the signals and provide an output of the 0 and l values serially. By taking the input or incoming signal and multiplying it by a generated split phase coded signal having a l value at the same frequency and phase relationship as the incoming signal, the l and 0 signals in the incoming signal can be detected by virtue of signal levels and be properly decoded. This is called locking of the incoming signal in the bit synchronizer. If the generated signal and incoming signal shift relative to one another by it is possible to falsely lock-in the signals, but in this case the decoding will be erroneous. In the event of a false lock-in, the generated signal is shifted by 180 to an in phase condition so that the proper decoding is obtained. If the frequency between the incoming signal and the generated signal are different, the frequency of the generated signal is adjusted to that of the incoming signal.

Referring now to FIG. 3, there is disclosed a bit synchronizing system for signals which are split phase bit coded. The system of FIG. 3 includes a voltage controlled oscillator 46 which generates a reference output frequency signal. A loop control system which controls VCO 46 provides for adjustment of the frequency of the generated signal to that of the incoming signals.

The decoded, serial output of bits which are synced to the generated frequency signal of the VCO 46 are issued from a storage circuit 23. v

The phase relationship of the generated and incoming signals are compared by a false lock detector 33 and, if necessary, the phase of generated signal is adjusted by 180 so that the serial'output of bits is correctly decoded;

The system is thus involved in adjusting the frequency of a generated signal to be the same as the frequency of an incoming signal, and adjusting the phase of a generated signal to be precisely in-phase with that of an incoming signal for proper decoding.

As illustrated in FIG. 3, a voltage controlled oscillator 46 provides a frequency output signal which can be varied in proportion to an input control error voltage.

The output of the VCO 46 is' supplied to a divide by two circuit 47 which halves the frequency for phase control purposes which will hereinafter be made more apparent. The output from the divider 47 is supplied to an exclusive OR circuit 48.The OR circuit 48 is controlled circuits 60 which provide timing and control outputs for the loop systems.

As will become apparent from the-discussion to follow, two loop circuits are employed for the detection of phase error and two other loop circuits are employed for the detection of false lock error. The first pair of loop circuits have an alternating operation which serves to provide an error signal for the VCO 46 for adjusting the frequency of the generated signal to a locked-in condition with resepct to the incoming signal. The other pair of loop circuits have an alternating operation which serves to provide comparison signals from which the false lock error signal can be derived.

To operate the system, a timing sequence is provided by logic circuit 60. The overall timing sequence is illustrated in FIG. 4 wherein FIG. 4(a) is a representation of an output from the OR circuit 48. The counter and logic circuit 60 provide the following outputs in response to the output from circuit 48:

a. a first in-phase alternating signal I, which is'shown in FIG. 4(b) as occurring between times t t and t.,-t and has a characteristic waveform representative of a l digit;

b. a second in-phase alternating signal l which is shown in FIG. 4(a) as occurring between times trtq and l t and has a characteristic waveform representative of a 1 digit;

c. a first quadrature alternating signal Q which is shown in FIG. 4(d) as occurring between times t t and t t and is shifted by 90 relative to the I, signal;

d. a second quadrature alternating signal O, which is shown in FIG. 4() as occurring between times [2"[4 and 1 -4 and is shifted by 90 relative to the I signal; 7

e a timing signal T, [FIG. 4(f)] which is one bit period long and is synchronized in time with the I, and I signals;

f. first and second dump signals D and D [FIG. 4(g)] where the D signal and D signal alternate for each bit period, and D signal being keyed to the bit period following the I, signal and the D signal being keyed to the bit period following the I signal the D, and D signals occurring just prior to the end of a bit period;

g1 first, second and third sampling pulses S S and S [FIG 4(h)] where the sampling pulse S, occurs just prior to the end of a bit period, the sampling pulse S occurs just at the start of a bit period, and the sampling pulse 8;, occurs intermediate of a bit period.

All of the foregoing pulses are timed or keyed to the I and I pulse times. Thus, if the OR circuit 48 shifts by 180 then the timing pulses will be shifted by 180.

For the detection of phase error and to maintain the frequency of the generated signals from the logic circuit 60 at the same frequency as the incoming signals, the incoming signal is multiplied with the quadrature signals Q1 and Q For example, in FIG. 5(a) an incoming signal 70 is illustrated where the signal has successive bits 70(A-F) which respectively occur during times ly-tg, tg-H, l try-t t and INT-I12- ln 5(b) the Q, quadrature signals 71A, 71 C and 71E respectively occur during times t t n-t and t t In FIG. 5(c) the Q quadrature signals 71B, 71D and 71F respectively occur during times t t-I t 't and -I When bit 70A and signal 71 A are multiplied and integrated over the time period t -t a double peaked response 72A is obtained ['FIG. 5(d)]. At time t the last value of the response is held for about three quarters of the next bit period and is illustrated as 72AA in FIG. 5 (d). At a time just prior to the time the dump signal D discharges the response 72AA in preparation for the next cycle of operation. Similarly, the signal 71C multiplied by signal 70C produces a response 72CC [FIG.

5(d)] which is held during the time period t -t as shown by 72CC. Just prior to time t,,, the dump signal D discharges the held value as indicated by 72CC. Likewise, the bit signal 71E multiplied by signal 70E produces a response 72EE [FIG 5(d)] which is'held during the time period t -t Referring now to FIG. 3, a Q, multiplier 40 is coupled v an integration and during the first part of the succeeding bit period, a sampling signal S supplied by the circuit 60 to the circuit 42 causes the signal potential existent and held in the circuit at that time to be passed to the switch 43. During the later part of this succeeding bit period, the dump signal D from circuit 60 discharges the signal from the hold circuit 42 in preparation for the circuit performing the next integration. The switch 43 is operated by the timing signal T to alternately couple the circuits 41 and 51 to a multiplier circuit 44.

Referring back to FIG. 5, the second, alternating Q signal as shown in FIG. 5(c) when multiplied by the incoming signal [FIG. 5(a)] similarly produces integration signals 72B, 72D and 72F which are respectively followed by hold signals 72BB, 72DD and 72FF. The signals 72BB, 72DD and 72FFare discharged by dump signals D, and the sampled signals obtained in response to the sample signals S, are supplied to the switch 43.

As FIG. 5(d) evidences, when the 0,, Q2 and incoming signals are in phase, the sampled output 73 [FIG. 5(e)] is level and the output of the VCO 46 is in frequency and phase synChronizationJWhen the Q and Q are out of phase with respect to the incoming signal, the frequency of the VCO will still be maintained constant. The reason for this is illustrated in FIG. 6 where the Q and Q signals of FIG. 6(b) and 6(0) are shifted 180 with respect to the illustration in FIG. 5. When the signals are multiplied, integrated, and held, the time of sampling occurs just after the times t t etc., so that a level sample output 74 occurs as shown in FIG. 6(e).

Whenever the Q signals and incoming signals are not in frequency and either 0 or 180 phase relationship, there is an error output produced during the sampling period which will produce a change in the frequency of the VCO 46 tending to drive the Q signals toward the frequency of the incoming signal and to a 0 or 180 phase locked condition. The error signal is supplied to the analog multiplier 44' which multiplies the signal by a 0 or 1" value as necessary to maintain the error signal at the same polarity. The 0" or l value obtained for the M s ignal is generated by the decoded 0 or 1" values from the I circuit.

Referring now to the 1 loop system, these are two channels which respectively supply signals to an output decoder circuit and to a false lock detector. The signals in each channel are integrated and the integration values are sampled just before and just after the end of a multiplication and integration operation for a bit period. Each channel is supplied with an in phase coded signal of one bit period duration which alternates with a quiescent period equal to one bit period.

Considering the first I loop system, the I multiplier 20 receives the I, signal [FIG. 7(b)] and the incoming signal [FIG. 7(a)] and passes the analog signal product to an integrate, hold, and dump circuit 21. With reference to FIG. 7, circuit 21 will multiply bits 70A and 80A, 70C and 80C, and 70E and 80E. The multiplication of 70A and 80A results in an integrated signal 82 A between the times t t At the time t the timing signal T (the end of a bit period) stops the integration and transfers the signal value 82 A to a hold circuit which provides a held value signal 82AA (at the last integration value) during the times t t until the dump signal D discharges the signal 82AA. At the time t the integration signal 82C is initiated and is stopped at time 1 to be followed by a held value signal 82CC which is discharged by the dump signal D just prior to the time t At the time I the integration signal 825 is initiated and is stopped at the time r and followed by the held value signal 83EE which is stopped by the dump signal D occurring just prior to the time I In the second I loop system, the I multiplier 30 receives the l signal [FIG. 7(d)] and the incoming signal [FlG. 7(a)] and passes the analog signal product to an integrate, hold, and dump circuit 31. Circuit 31 will multiply bits 708 and 80B, 70D and 80D, and 70F and 80F. The multiplication of 70B and 80B results in an integrated signal 828 between the times t -t At the time t.,, the timing signal T (the end of a bit period) stops the integration and transfers the signal value 82B to a hold circuit which provides a held value signal 82BB (at the last integration value) during the times 1 -1 until the dump signal D discharges the signal 8288. At the time 1 the integration signal 82D is initiated and is stopped at the time t to be followed by a held value signal 82DD which is discharged by the dump signal D just prior to the time r At the time t the integration signal 82F is initiated and is stopped at the time and is followed by a held value signal 82EE which is stopped by the dump signal D,.

From the foregoing it will be appreciated that when the l and I signals are correctly in-phase with the incoming signals, the first 1 channel during one bit period develops a positive sloped integrated signal for bit values of l and a negative sloped integrated signal for bit values of 0 following each integration, and in the succeeding bit period the held value of the integration is either positive for a l or negative for a 0 bit value. In the second I channel while an integration value is being held in the first channel, the second channel performs an integration over a bit period. At the end of the bit period for integration in the second channel, the integrated value is held while the first channel begins an integration.

The first channel circuit 21 is coupled by an output 21a to a switch 22 and the second ch'annelcircuit 31 is coupled by an output 31a to the switch 22. The switch 22 is operative for each bit period to be coupled to one of the circuits 21 or 31. The drawings illustrate that if circuit 21 is synced to bits 80A, 80C, etc., then the switch would be alternatively coupled to integration of the signals respectively and alternatively in the first and second channels as illustrated in FIG. 7Q).

Circuits 21 and 31 are made responsive to a sampling pulse S [see FIG. 7(f)] which occurs just prior to the end of a bit period. The sampling pulses, and switch 8 22 cooperate to alternatively pass a sampled signal voltage to the storage circuit 23. The storage circuit 23 is responsive to a sampled pulse to produce a level output until the next sampled input signal. As shown in FIG. 7(h), a signal 84A results from the sample taken at the time S, from signal 82A [FIG. 7(f)]. In FIG. 7(h), the signals 84B, 84C, 84D and 84E correspond to sampled signals 82B, 82C, 82D and 82E. As would be expected, at the sampling time just prior to the time t,, the signal 82D is negative and a negative response occurs. This response is indicative of an 0 bit and the detection is at the end of the bit period for the 0 bit.

The second channel circuit 31 is coupled by an output 31b to a switch 32 and the first channel circuit is coupled by an output 21b to the switch 32. The switch 32 is operative for each bit period to be coupled to one of the circuits 21 or 31 by virtue of the input switching pulse T,. The drawings illustrate that if circuit 31 is synced to bits 808, D, etc., then the switch would be alternately coupled to the held values of the signals occurring in the bit period immediately following integration.

Switch 32 alternatively couples the held signal values from the first and second channels as illustrated FIG. 7(g). Circuits 21 and 31 are made responsive to a sampling pulse S, [see FIG. 7(g)] which occurs just at the start of a bit period. The sampling pulse S, and switch 32 cooperate to alternatively pass a sampled signal voltage to a storage circuit 34 which outputs to the false lock detector circuit 33. The detector circuit 33 is responsive to the voltage signal sampled by the pulse S, and the voltage signal sampled by the pulse 5,.

As shown in FIG. 7(g), the heldvalue signals 82AA, 82BB, 82CC, 82DD, etc. are respectively available to switch 32. At the sampling time S, in the bit period immediately following the bit period of integration, the sampled and held potential is passed through the switch 32 at the signal levels illustrated by the signals 82AA, 828B, 82CC, and 82DD and so forth. As evidenced by FIG. 7(i), the signal 85D is relatively negative as the held sample value is relatively negative. The signals as represented by FIGS. 7(h) and 7(i) are supplied to the false lock detector 33. Detector 33 operates on the principle that if the relative value of the input signals is the same, there is no output. An input sampling pulse S occurring at the midpoint for a synced signal samples the input signales to the detector 33. Thus, for each of the sampling periods S; as shown in FIG. 70), the inputs have the same relative values and there is no output from the detector 33 which is indicative of the correct in phase relationship of the I and incoming signals.

Referring now to FIG. 8, an example is given where the incoming signal is 180 out of phase with respect to the I generated signal. The I signals shown in FIG. 8(c) and FIG. 8(d) are shifted to the left by 180. Thus, multiplication and integration of the product of signal bit 908 with the last bit half of bit 70A and the first bit half of bit 708 provides the waveform 92B as shown in FIG. 8(e). Multiplication and integration of the'product of signal D with the last bit half of signalbit 70C and the first bit half of signal bit 70D produces a V shaped integration signal 92D. Multiplication and integration of the product of signal 900 with the last bit half of signal bit 70C and the first bit half of signal bit 70D produces a V shaped integration signal 92D.

Multiplication and integration of the product of signal 90F with the last bit half of signal bit 70E and the first bit half of signal bit 70E produces the negatively sloped waveform 92F as shown in FIG. 8(a). The multiplication and integration of the product of signal 90E with the last half bit period of signal 70D and the first half bit period 70E results in a rooftop shaped integration signal 93E, as shown in FIG. 8(0). As illustrated in FIG. 80), switch 22 will see the alternate integrations while in FIG. 8(g), the held values of the signals to switch 32 are illustrated. At the sample times S for FIG. 8Q), the storage circuit 23 produces signals 94-94E as shown in FIG. 8(h), for example. At the S, sample time just prior to the time t,;, the signal 92 D is negative and at the sample time S just prior to time 2, the signal 92E is positive. Signal 92E accordingly produces a positive output 94E from the circuit 23. At the sample times S signals 95A-95E [FIG. 8(i)] are produced by the storage circuit 34. The signal 95D is positive because at the time t, the signal 92DD is at zero potential. Signal 95E is also positive because at the S time following the time the signal 92EE is at zero potential. The detector 33 produces an output pulse 98 at a time t because the sample pulse S finds the signal 95D positive relative to the signal 94D. At the time t both signals 94E and 95E are positive and no output is produced by the detector 33.

Referring now to FIG. 9, a plot of the error voltage developed by the Q loop systems as a function of phase error is illustrated. At 0 and 180, the error represented by the error 99 is nulled at a zero output. As the phase error increases to 90 to 270, the error output sensitivity increases. From this it can be appreciated that the magnitude of the correction signal to the VCO 46 is a function of phase error.

In the operation of the present invention, incoming split phase coded signals are supplied to each of the I multiplier circuits 20 and 30 and each of the Q multiplier circuits 40 and 50. By definition, the incoming signals are either I and 0" values dependent upon whether the first half of the signal for a bit period is positive or negative. The generated signals consist of I signals which are representative of a l value and Q signals which are representative of an I signal shifted in phase by 90. Two channels are arranged to operate alternately and provide an error control signal for controlling the frequency of the generated signal from the VCO 46 relative to the incoming signal and to null the generated and incoming signals in either a 0 or l80' locked relationship whenever the frequencies are equal.

The frequency control is obtained by multiplying the incoming signal in a first channel by a first series of generated O signals which occur every other bit period, in-

tegrating each multiplication and holding the existentvalue of the integration at the end of each bit period during which the multiplication step occurs. In the quiescent bit period following the multiplication and integration, the held value is sampled for the first channel. The incoming signal is also multiplied in a second channel by a second series of generated 0 signals which occur every other bit period in alternation with the first series of signals. The multiplication product in the second channel is integrated over the bit period, and at the end of this bit period the existent value of the integration is held during the following quiescent bit period. During this quiescent bit period, the held value is sampled for the second channel. If the incoming and Q signals have the same bit period, i.e., the same. frequency, and are in either 0 or phase locked condition, the held value output will be constant.

If the incoming signal and 0 signal shift phasewise from the null conditions at 0 and 180, the held value during the quiescent periods increases or decreases as a function of the relative lead or lag of the signals. Similarly, if the signals have different frequencies, there will be a phase difference which produces a correction error output. The VCO 46 changes the frequency until the frequencies of the incoming signal and Q signals are in phase.

Whenever the incoming signals and Q signal are at the same frequency, the signals can lock-up at either a 0 or 180 phase relationship of the incoming and I signals without shifting the frequency output of the VCO 46. At this condition point of operation, the incoming signal is multiplied in a first I channel by a first series of alternately in phase generated I signals which occur every other bit period. The multiplication produce during the bit period that the I signal occurs is integrated over this bit period. During this bit period, the integration signal is supplied to a first switch 22 and to a second switch 32. Just prior to the end of this bit period, a sample signal is taken at time S, and passed by the first switch circuit 22 to a storage circuit 23. Atthe end of this bit period, the first switch 22 is disconnected from the first I channel and connected to the second I channel. Also, at the end of the described bit period, the second switch 32 transfers the last stored or held integration value of the signal during the following quiescent bit period. just after the initiation of the next following period, a sample signal is taken at a time S of the held value of the signal and this signal is passed to the false lock detector 33.

Essentially, what is occurring is that with regard to a synced I signal, a sample is taken just before and just after the time at which a timing signal occur s. If the incoming signal is at'the same frequency and phase relationship, then the integrated and held values of the generated and incoming bit are similar and the detector produces no phase correction output signal. If, however, a phase difference occurs then the sampled signals produce a differential which causes the detector 33 to operate the flip-flop 49 and change the phase of the timing signals by 180.

In brief summary of the system embodying the present invention, there is a signal generating means which includes the VCO 46, the divide by two circuit 47 the exclusive OR circuit 48, and the ring binary counter and logic means 60. To control the VCO 46, parallel channels receive the incoming inputs of data word phase coded signals and multipliers 40 and 50 respectively combine generated signals from the logic means 60 with the incoming signals. Switch means '43 provide successively occurring error output signals whenever the signals are not in a phase-locked condition, the error signals serving to adjust the VCO 46 so that the frequency and phase output of the logic means 60 are adjusted to that of theincoming signals and the signals will lock up on eiter a 0 or 180 condition.

In the decoding loop circuit there are parallel electrical channels respectively having multipliers 20 and 30 for combining incoming inputs of data word signals with generated I signal from the logic means 60.'Because the I signals alternately occur, each of the circuit means 21 and 31 integrates a combined signal for one time frame and holds the integrated value during the succeeding time frame. The switch 22 provides a first series of interleaved data signals which are keyed to timing signals occurring just before the start of a time frame. The switch 32 provides a second series of interleaved data signals which are keyed to timing signals occurring just after the start of a time frame. The two outputs of the switches 22 and 32 are received by a false lock detector means 33 and a sampling time inter mediate of a time frame determines if the incoming and generated I signals are in phase or 180 out of phase. If out of phase, then the detector means 33 controls the generating means by changing the output of the OR circuit 48 by 180.

While particular embodiments of the present invention have been shown and described, it is apparent that changes and modifications may be made without departing from this invention in its broader aspects; and, therefore, the aim in the appended claims is to cover all such changes and modifications as fall within the true spirit and scope of this invention.

What is claimed is: 1. In a data processing system which receives incoming data word signals comprised of bits, each bit having a phase code modulation characteristic indicative of a digit value,

means for demodulating said word data signals and for synchronizing the bits of an incoming data word relative to the phase code modulation characteristic including: means for generating phase coded signals representative of a given digit value, first means including first parallel electrical channels for respectively combining incoming inputs of data word phase coded signals representative of bit values with said generated signals, and for providing error output signals whenever said combined signals are not in a phaselocked condition, said generating means being responsive to said error output signals to adjust said generated signals toward a phase-locked condition for said combined signals, second means including second parallel electrical channels for respectively combining incoming inputs of data word phase coded signals representative of bit values with said generated signals, and for providing first and second series of interleaved data signals, said interleaved data signals respectively being a function of alternately occurring bits of said data word signals,

means for sampling said interleaved. data signals at given times within each time frame for a bit for determining the presence or absence of a phase-locked condition, and for controlling said generating means so that the phase of said generated signals is locked to a 0 phase-locked condition with respect to said incoming input signals. 2. The system of claim 1 wherein said combining means in said second channels'are analog multiplier means and said second means includes switch means for providing said first and second series of interleaved data signals.

3. The system of claim 2 wherein said channel means further including means for integrating the output of said multiplier means, means for limiting the integration time in each channel to a time frame for bit, means for retaining an integration signal during a time frame succeeding an integration time frame.

4. The system of claim'3 wherein said combining means in said first channels are analog multiplier means, and said first means includes switch means for providing successively occurring error output signals whenever said combined signals are not in a phaselocked condition.

5. The system of claim 4 wherein said sampling means further including means for receiving said two outputs and wherein said sampling times intermediate of a time frame for a bit are keyed for determining the phase-locked condition.

6. The system of claim 5 wherein said means for receiving said two outputs provides a phase change signal generating means for changing the phase of said gener ating signals by 180.

7. In a data processing system which receives incoming data word signals comprised of bits, each bit having a phase code modulation characteristic indicative of a digit value,

means for demodulating said word data signals and for synchronizing the bits of an incoming data word relative to the phase code modulation characteristic including: first loop means including means for receiving income data word signals and for generating data signals representative of a given digit value, said first loop means including means for locking the generated data signal to said incoming wordsignals in either a 0 or l phase relationship, second loop means for combining income data word signals and said generated data signals for providing a first and second series of combined signals, said first series of combined signalscomprising first alternately occurring bit values, said second series of combined signals representing second alternately occurringv signals representative of second alternately occurring bit values, means forsampling said combined signals during each time period for a bit value for providing sample signals,

means for comparing said sampled signals fromfirst and second series of signals and for providing phase adjustment signals to said first loop means .for maintaining the incoming data word signals in at 0 locked phase relationship with respect to said generated data signals. I

8. The system of claim 7 wherein the second loop means includes parallel electrical channels each including multiplier means, means responsive to the output-of said multiplier means for integrating the multiplier output for each time period for a bit value and for holding an integrated value during a succeeding time period for such a bit value. 

1. In a data processing system which receives incoming data word signals comprised of bits, each bit having a phase code modulation characteristic indicative of a digit value, means for demodulating said word data signals and for synchronizing the bits of an incoming data word relative to the phase code modulation characteristic including: means for generating phase coded signals representative of a given digit value, first means including first parallel electrical channels for respectively combining incoming inputs of data word phase coded signals representative of bit values with said generated signals, and for providing error output signals whenever said combined signals are not in a phaselocked condition, said generating means being responsive to said error output signals to adjust said generated signals toward a phase-locked condition for said combined signals, second means including second parallel electrical channels for respectively combining incoming inputs of data word phase coded signals representative of bit values with said generated signals, and for providing first and second series of interleaved data signals, said interleaved data signals respectively being a function of alternately occurring bits of said data word signals, means for sampling said interleaved data signals at given times within each time frame for a bit for determining the presence or absence of a 0* phase-locked condition, and for controlling said generating means so that the phase of said generated signals is locked to a 0* phase-locked condition with respect to said incoming input signals.
 2. The system of claim 1 wherein said combining means in said second channels are analog multiplier means and said second means includes switch means for providing said first and second series of interleaved data signals.
 3. The system of claim 2 wherein said channel means further including means for integrating the output of said multiplier means, means for limiting the integration time in each channel to a time frame for bit, means for retaining an integration signal during a time frame succeeding an integration time frame.
 4. The system of claim 3 wherein said combining means in said first channelS are analog multiplier means, and said first means includes switch means for providing successively occurring error output signals whenever said combined signals are not in a phase-locked condition.
 5. The system of claim 4 wherein said sampling means further including means for receiving said two outputs and wherein said sampling times intermediate of a time frame for a bit are keyed for determining the phase-locked condition.
 6. The system of claim 5 wherein said means for receiving said two outputs provides a phase change signal generating means for changing the phase of said generating signals by 180*.
 7. In a data processing system which receives incoming data word signals comprised of bits, each bit having a phase code modulation characteristic indicative of a digit value, means for demodulating said word data signals and for synchronizing the bits of an incoming data word relative to the phase code modulation characteristic including: first loop means including means for receiving income data word signals and for generating data signals representative of a given digit value, said first loop means including means for locking the generated data signal to said incoming word signals in either a 0* or 180* phase relationship, second loop means for combining income data word signals and said generated data signals for providing a first and second series of combined signals, said first series of combined signals comprising first alternately occurring bit values, said second series of combined signals representing second alternately occurring signals representative of second alternately occurring bit values, means for sampling said combined signals during each time period for a bit value for providing sample signals, means for comparing said sampled signals from first and second series of signals and for providing phase adjustment signals to said first loop means for maintaining the incoming data word signals in a 0* locked phase relationship with respect to said generated data signals.
 8. The system of claim 7 wherein the second loop means includes parallel electrical channels each including multiplier means, means responsive to the output of said multiplier means for integrating the multiplier output for each time period for a bit value and for holding an integrated value during a succeeding time period for such a bit value. 